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| SL74HCT163 Presettable Counters High-Performance Silicon-Gate CMOS The SL74HCT163 is identical in pinout to the LS/ALS163. The SL74HCT163 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The SL74HCT163 is programmable 4-bit synchronous counter that feature parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The SL74HCT163 is binary counter with synchronous Reset. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION SL74HCT163N Plastic SL74HCT163D SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 16 =VCC PIN 8 = GND Inputs Reset L H H H H X Load X L H H H X Enable P X X X L H X FUNCTION TABLE Outputs Enable T X X L X H X Clock Q0 L P0 Q1 L P1 Q2 L P2 Q3 L P3 Function Reset to "0" Preset Data No count No count Count No count No change No change Count up No change X=don't care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3 SLS System Logic Semiconductor SL74HCT163 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT163 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 4.0 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 40 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 160 A A V Unit VIH VIL VOH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V V V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND VIN=VCC or GND IOUT=0A VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A ICC -55C 25C to 125C 2.4 mA 5.5 2.9 SLS System Logic Semiconductor SL74HCT163 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tTLH, t THL CIN Maximum Propagation Delay, Clock to Ripple Carry Out (Figures 1,6) Maximum Output Transition Time, Any Output, (Figures 1 and 6) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC+ICCVCC Parameter Maximum Clock Frequency (Figures 1,6) Maximum Propagation Delay, Clock to Q (Figures 1,6) Maximum Propagation Delay, Enable T to Ripple Carry Out (Figures 2,6) 25 C to -55C 30 34 41 32 39 35 43 15 10 85C 24 43 51 40 49 44 54 19 10 125C 20 51 62 48 59 53 65 22 10 Unit MHz ns ns ns ns ns ns ns pF Typical @25C,VCC=5.0 V 60 pF TIMING REQUIREMENTS (VCC=5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol tsu tsu tsu tsu th th th th trec tw tw tr, tf Parameter Minimum Setup Time, Preset Data Inputs to Clock (Figure 4) Minimum Setup Time, Load to Clock (Figure 4) Minimum Setup Time, Reset to Clock (Figure 3) Minimum Setup Time, Enable T or Enable P to Clock (Figure 5) Minimum Hold Time, Clock to Preset Data Inputs (Figure 4) Minimum Hold Time, Clock to Load (Figure 4) Minimum Hold Time, Clock to Reset (Figure 3) Minimum Hold Time, Clock to Enable T or Enable P (Figure 5) Minimum Recovery Time, Load Inactive to Clock (Figure 4) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 4) Maximum Input Rise and Fall Times (Figure 1) 25 C to -55C 30 27 32 40 10 3 3 3 25 16 16 500 85C 38 34 40 50 13 3 3 3 31 20 20 500 125C 45 41 48 60 15 3 3 3 38 24 24 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns SLS System Logic Semiconductor SL74HCT163 SLS System Logic Semiconductor SL74HCT163 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Test Circuit SLS System Logic Semiconductor SL74HCT163 VCC=Pin 16 GND=Pin 8 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flipflop low. Figure 7.Expanded logic diagram SLS System Logic Semiconductor SL74HCT163 Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 8. Timing Diagram SLS System Logic Semiconductor SL74HCT163 TYPICAL APPLICATIONS CASCADING Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and clock. Figure 9. N-Bit Synchronous Counters Figure 10. Nibble Ripple Counter SLS System Logic Semiconductor |
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